1. Field of the Invention
The present invention relates to high density memory devices based on phase change materials like chalcogenides and others, and to methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous solid phase and a crystalline solid phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data. Thus, phase change materials can be characterized as a type of programmable resistive memory material. These properties have generated interest in using phase change material and other programmable resistive memory material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause the transition of the phase change material from a crystalline state to an amorphous state. The memory cells using phase change material include an “active region” in the bulk of the phase change material of the cell in which the actual phase transitions are located. Techniques are applied to make the active region small, so that the amount of current needed to induce the phase change is reduced. Also, techniques are used to thermally isolate the active region in the phase change cell so that the resistive heating needed to induce the phase change is confined to the active region.
The magnitude of the reset current needed for reset can also be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.
One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalcogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.
Another technology developed by the assignee of the present application is referred to as a phase change bridge cell, in which a very small patch of memory material is formed as a bridge across a thin film insulating member located between electrodes. The phase change bridge is easily integrated with logic and other types of circuitry on integrated circuits. See, U.S. application Ser. No. 11/155,067, filed 17 Jun. 2005, entitled “Thin Film Fuse Phase Change RAM and Manufacturing Method,” by Lung et al., incorporated by reference as if fully set forth herein, which application was owned at the time of invention and is currently owned by the same assignee.
Yet another approach to controlling the size of the active area in a phase change cell is to devise very small electrodes for delivering current to a body of phase change material. This small electrode structure induces phase change in the phase change material in a small area like the head of a mushroom, at the location of the contact. See, U.S. Pat. No. 6,429,064, issued Aug. 6, 2002, to Wicker, “Reduced Contact Areas of Sidewall Conductor;” U.S. Pat. No. 6,462,353, issued Oct. 8, 2002, to Gilgen, “Method for Fabricating a Small Area of Contact Between Electrodes;” U.S. Pat. No. 6,501,111, issued Dec. 31, 2002, to Lowrey, “Three-Dimensional (3D) Programmable Device;” U.S. Pat. No. 6,563,156, issued Jul. 1, 2003, to Harshfield, “Memory Elements and Methods for Making Same.”
In co-pending U.S. Patent Application entitled PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING; application Ser. No. 11/855,983; filed 14 Sep. 2007; which is incorporated by reference as if fully set forth herein, a representative mushroom memory cell and manufacturing process are described in detail.
Manufacturability of integrated circuit memory devices, such as phase change memory devices, requires that efficient testing methodologies be provided for use during manufacturing. For example, it is desirable to detect faulty devices during manufacturing, such as before packaging of the individual die, in order to avoid packaging defective devices and wasting the expense of such packaging. Also, it is desirable to detect faulty devices during manufacturing, so that the manufacturing process can be tuned to improve yield.
Testing methodologies can require significant processing overhead for large scale integrated circuit devices, and can slow down the manufacturing process. Thus it is desirable to provide methodologies that provide good information with low processing overhead.